TSMC Selects Silicon Canvas' Laker T1 as Its Test Chips Development Automation Platform

San Jose, Calif., December, 12, 2002 -- Silicon Canvas, Inc. (SCI), an EDA company that provides test chip development platform and next-generation custom layout solutions, today announced Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) (NYSE: TSM), the world's largest dedicated chip foundry, selects its Laker T1 as TSMC's automation platform for test chips development. With Laker T1, TSMC has built a production flow, which demonstrates more competitiveness in developing test chips for its technology development.

" We are glad that the partnership with Silicon Canvas has further boost TSMC's competitiveness in technology development. The synergy created by our R&D team and SCI's Laker T1 platform has shortened the timing of developing new test chips. In addition, our production flow combining Laker T1 has made it easier to standardize, parameterize and reuse the test structures to accommodate any new process requirements," says Dr. K.L. Young, director of Research & Development at TSMC.

"In working with TSMC, we've been very impressed by the caliber of their R&D team, and their dedication to quality and their commitment to provide the best advanced process. The pressure is tremendous on TSMC's R&D teams to meet the aggressive test chip tape out schedule and deliver advanced technology node" according to Dr. Hau-Yung Chen, president at Silicon Canvas, Inc. "Through Laker T1, Silicon Canvas offers automation and correct by construction test chip layout implementation resulting not only in huge time savings, but, just as importantly, a solid and verifiable test chip development platform. This is a major milestone for Silicon Canvas in the foundry customer. Our innovative R&D efforts have again extended the performance to keep pace with our customers' demanding schedules."

About Laker T1:
The Laker T1 system is particularly well positioned to specialize in test chip development automation. It's a platform to delivers a ten-fold productivity gain through automation, reusable, transferable and manageable with centralized access control. Laker T1 provides an easy way to define reusable parameterized test structures and test lines. The user defined parameterized test structures can easily cover process, reliability and Spice test devices. Customers can use them and realize an error-free test line in minutes. It also generates a user configurable test chip document and links to test equipments. Customer can ensure the consistence among concept, layout, document and test program on this platform.

Laker T1 is available now for Unix and Linux machine.

About Silicon Canvas:
Silicon Canvas is the technology leader in providing test chip development platform and full-custom layout solutions for products and services. Founded in 2000 by Dr. Hau-Yung Chen in conjunction with other EDA veterans with combined over 50+ years of experience. The company's custom layout tool, Laker, addresses the ever-important needs of today's analog, mixed-signals, large complex IC, ASIC, and SoC designs. Silicon Canvas' custom layout solutions provide more automation and high performance capabilities to any design projects, which require the use of more effective full-custom layout solutions, including but not limited to the layout creation for analog, mixed-signals, and test chip designs, etc. Customers' applications include processors, computing systems, networking, telecommunication and graphics.

Silicon Canvas, Inc is located in San Jose, California. For more information, you can visit our website at www.sicanvas.com or send an email to info@sicanvas.com. Feel free to contact us at (408) 392-0288.

About TSMC
TSMC is the world's largest dedicated semiconductor foundry, providing the industry's leading process technology and the foundry industry's largest portfolio of process-proven library, IP, design tools and reference flows. The company operates one advanced 300mm wafer fab, five eight-inch fabs and one six-inch wafer fab. TSMC also has substantial capacity commitments at two joint ventures fabs (Vanguard and SSMC) and at its wholly-owned subsidiary, WaferTech. In early 2001, TSMC became the first IC manufacturer to announce a 90-nanometer technology alignment program with its customers. TSMC's corporate headquarters are in Hsin-Chu, Taiwan. For more information about TSMC, please visit http://www.tsmc.com.

For more information, please contact:

Silicon Canvas, Inc.
Hau-Yung Chen
1762 Technology Drive,
Suite 225, San Jose, CA95110
Phone: 1 408.392.0288
Fax: 1 408.392.0289
E-mail: hchen@sicanvas.com